Computer Systems Simulation

Major: Computer Engineering
Code of subject: 6.123.00.O.121
Credits: 4.00
Department: Specialized Computer Systems
Semester: 4 семестр
Mode of study: денна

Computer Systems Simulation

Major: Computer Engineering
Code of subject: 6.123.00.O.120
Credits: 4.00
Department: Electronic Computing Machines
Lecturer: senior lector of ECM department Tsygylyk Liubomyr Orestovych
Semester: 4 семестр
Mode of study: денна
Learning outcomes: As a result of studying this course, the student should be able to demonstrate the following learning outcomes: • know basic types of computer systems models; • know the VHDL hardware description language; • know the Verilog hardware description language; • know the technology to create, model and synthesize new projects using hardware description languages; • design the architecture of systems and individual modules using HDL tools; • perform the analysis of the task independently, make the choice of the necessary modules to describe the computer system; • create a model of a computer system, validate it and obtain simulation results, model the synthesis on the hardware FPGA. The study of the course involves the formation and development of competencies in students: common: in the field of hardware systems design, behavior modeling (logical), they should know information about the list of hardware systems design tools. professional: analyse the given task and make desition how to develop and modeling a system (module) architecture using HDL languages.
Required prior and related subjects: Previous courses: 1. Applied theory of digital vending machines; 2. Computer electronics; 3. Computer circuitry. Related and following courses: 1. Computer Circuitry, Course work; 2. Fundamentals of CPU design for FPGA; 3. Bachelor and diploma projects.
Summary of the subject: Modeling of the computer systems involves learning hardware description languages, such as VHDL and Verilog. This discipline provides a detailed overview of the purpose, usage and handling of VHDL and Verilog. The lab work covers key aspects of the VHDL hardware description language such as: • announcement of signals, ports, processes; • work with cycles and conditional operators; • functions and procedures; • system modeling and error tracking method. Practical classes include working with students in an interactive format. The basis of the practical classes is the organization of the student's thinking to solve the task.
Assessment methods and criteria: Control: practical and laboratory study, verbal questioning (totally 30 %); Final control: (70%): examination testing and writing program code.
Recommended books: 1. EVITA Enhanced VHDL Tutorial with Application. Rev. 2.1. Aldec Inc. – Electronic library of ECM departament. 2. EVITA Enhanced Verilog Tutorial with Application. Rev. 1.0. Aldec Inc. – Electronic library of ECM departament. 3. Zainalabedin Navabi. VHDL: Analysis and Modelling of Digital Systems. – McGraw-Hill Inc., USA, 1992. 4. Algorithm Design for Networked Information Technology Systems, Samit Ghosh, USA, 2003 5. Khomych S.V. Hardware description lenguages. Course of lectures. – Electronic library of ECM departament., 2005.